The present invention relates to a semiconductor memory device and, more particularly, to an asynchronous static semiconductor memory device.
A conventional asynchronous static semiconductor memory device (to be referred to as a static memory hereinafter) has high power consumption. In order to decrease the power consumption, there has been developed a pulse word system as described in Japanese Utility Model Application No. 57-7267, wherein a word line and a sense amplifier are activated in response to an internal clock for a predetermined period of time upon address updating to latch readout data via a latching circuit, and wherein thereafter the word line and the sense amplifier are rendered inactive.
A typical circuit arrangement of the pulse word system is shown in FIG. 1. Referring to FIG. 1, reference numeral 1 denotes a memory cell matrix having M (rows).times.N (columns) of memory cells MC. Each memory cell MC is connected to a corresponding word line WLj (j=0, 1, . . . M) and a pair of digit lines DGk and DGk (k=0, 1, . . . N). Reference numeral 2 denotes a gate circuit connected to the digit lines DGk and DGk and comprising switching gates Gk (k=0, 1, . . . N) each selecting one of the signals from the digit lines DGk and DGk. Reference numeral 3 denotes a digit line load circuit comprising load transistors LDk (k=0, 1, . . . N) each of which is connected to one end of each of the digit lines DGk and DGk.
An output from each switching gate Gk in the gate circuit 2 is connected to a sense amplifier 4. When the amplifier AMPk in the sense amplifier 4 receives a control signal SE, an amplified digit signal is generated therefrom. Reference numeral 5 denotes a latching circuit connected to the outputs of the sense amplifier 4. When a control signal DOE is applied to the latching circuit 5, it latches a signal supplied thereto. Reference numeral 6 denotes an output circuit each of which receives an output signal from the latching circuit 5 and generates an output DOUTk. Reference numeral 7 denotes an input buffer which is connected to the digit lines DGk and DGk to supply an input signal at an input terminal DIN to the digit lines.
Reference numeral 8 denotes an X address decoder; and 9, a Y address decoder. Outputs from the X and Y address decoders 8 and 9 are connected to the word line WLj (j=0 to M) and the gate Gk of the gate circuit 2.
Reference numeral 10 denotes an internal control circuit which comprises an address buffer 11, an address transfer detector 2, and an internal control signal generator 13. The address buffer 11 receives an address input Ai (where Ai is the ith bit signal) and generates a pair of complementary signals Ai' and Ai'. The outputs from the address buffer 11 are supplied to NOR gates 8-j (j=0 to M) in the X address decoder 8 and NOR gates 9-k (k=0 to N) in the Y address decoder 9.
The address transfer detector 12 detects an address transfer on the basis of the signal from the address buffer 11 and supplies an address transfer detection signal AEi to the internal control signal generator 13.
The internal control signal generator 13 generates internal control signals WDE, SE and DOE in accordance with the signal AEi supplied from the address transfer detector 12. The control signal WDE is connected to the NOR gates 8-j in the X address decoder 8 and is called a word drive signal. The control signal SE is connected to the sense amplifier 4 and is called a sense enable signal. The control signal DOE is connected to the latch circuit 5 and is called a latch signal.
The general operation of the circuit described above will now be described with reference to the timing charts of FIGS. 2A to 2E which illustrate system waveforms when an input signal of low rise (fall) time is applied to the above circuit. In FIGS. 2A to 2E, signals are plotted along the same time base. When the address input Ai is updated, outputs Ai and Ai' from the address buffer 11 are also updated, thereby causing the address transfer detector 12 to generate the address transfer detection signal AEi. In response to the signal AEi, the word drive signal WDE goes low to enable the X address decoder 8. The voltage level of the selected word line WLj is set at the high level. In the gate circuit 2, the transistor Gk selected by the Y address decoder 9 is turned on. A data signal from the selected memory cell MC appears on the digit lines DGk and DGk, and is supplied to the amplifier AMP in the sense amplifier 4 through the transistor Gk in the gate circuit 2. When the data signal is supplied to the sense amplifier 4, the sense enable signal SE goes high, thereby enabling the amplifier AMP in the sense amplifier 4 and hence amplifying the readout data. After the sense amplifier 4 is enabled, the latching circuit 5 is reset. When sufficiently large signals SD and SD appear from the sense amplifier 4, the latch signal DOE goes high to enable the latching circuit 5. Thereafter, the signals SE and WDE go low.
During the operation sequence described above, the order of activation of the word line WLj, the sense amplifier 4 and the latching circuit 5 is critically important, and must be maintained even when the rise and fall times of the input signal are long, a factor not considered in the conventional circuit. When this sequence is not properly performed, a system failure occurs. FIGS. 3 to 5 show improper sequences which may result from a failure to consider rise (fall) time variances. The voltage VIN of the address signal Ai is plotted along the abscissa, and the voltage levels of the signals WDE, SE and DOE are plotted along the ordinate. Referring to FIG. 3, a voltage range V1.ltoreq.VIN.ltoreq.V2 for enabling the X address decoder 8, a voltage range V3.ltoreq.VIN.ltoreq.V4 for precharging the latching circuit 5, and the voltage V5 representing a logic threshold value at which the output from the X address decoder 8 changes, satisfy the inequality V3&lt;V1&lt;V5&lt;V2&lt;V4. Every time the latching circuit 5 is enabled, irrespective of the logical transition from high level to low level or vice versa of the address input voltage VIN, the sense amplifier 4 and the X address decoder 8 are already disabled, so that the input to the latching circuit 5 is indefinite. For this reason, the latching circuit 5 may latch improper data. In the case of FIG. 4, since the inequality V1&lt;V5&lt;V3&lt;V4&lt;V2 is established, no error occurs when the voltage VIN goes from low to high. However, when the voltage VIN goes from high to low, the latching circuit 5 latches the data before the output from the X address decoder 8 is updated. For this reason, the data accessed by the selected address cannot be properly generated. In the case of FIG. 5, the inequality V5&lt;V1&lt;V3&lt;V4&lt;V2 is established. An output from the X address decoder 8 which corresponds to the lower bits of the address signal cannot be selected. As a result, read and write access cannot be performed.
As is apparent from the above operation, the sequence of the internal control signals is very important in the pulse word system. In Japanese Utility Model Application No. 57-7267, when the transient time (i.e., the rise or fall time of the input signal) is shorter than 20 nsec, the operation can be properly performed. However, no allowance is made for operations when the rise or fall time is long (e.g., 100 nsec or longer). In an asynchronous static memory, proper operation is required irrespective of the length of the rise and fall times of the input signal. Therefore, a failure in read/write access in the conventional asynchronous static memory of the pulse word system due to the length of the rise or fall time of the input signal presents a critical problem.